Hardware Intel talks about Nehalem, Larrabee & 32nm

http://www.bit-tech.net/hardware/2008/03/19/intel_talks_nehalem_larrabee_and_32nm/1

Earlier in the week, we chatted to Intel ahead of next month's Intel Developer Forum to discuss some of its future products... Nehalem and Larrabee to be specific. It looks like 2009 and onwards will see all the major players fight on multiple fronts.

 

peta flops ey?

 

Will AMD ever catch up???

 

Finally an integrated memory controller on the chip

 

Time's going AMD, tick, tock

 

as somone who does alot of work on small microproccesors and some FPGA work these things are unbelivably insanly fast and high-tech. They must have run right upto the transitor budget for the cache to be cut as it's a big PR number (although I would rather have on die memory controllers and optimisations like they have done).

 

just a question, AMD brought out phemon a while ago right? then why are we hearing about a release coming up? is it some sort of rerelease that will fix the problems with the current architecture? like being able to scale past 3 ghz?

 

The release is for the B3 stepping which fixes the TLB errata in the hardware without causing performance degredation (unlike the BIOS patch). Any performance gains i.e. overclocking haven't been reviewed yet except for a 'first look' over at anandtech.

Oh yeah, it's also the release of the higher clocked models that were pulled from the original launch, 9750 and 9850.

 

Why a 3 channel DDR3 controller? Does that mean we will get motherboards with support for up to 6 memory slots?
http://www.bit-tech.net/content_images/2008/03/intel_talks_nehalem_larrabee_and_32nm/neh7-8.jpg
Larrabee sounds interesting though I can't see them killing Nvidia for some time (AMD/ATI may be a different matter though)

 

cool thanks, the b3's are 3 cores though arent they? are there quads with this fix as well?

 

For the first question, no. B3 is just the silicon stepping to help address problems from previous silicon designs and in some cases increase performance. The tri-cores will most likely launch with this stepping as they are just quads with a faulty core that didn't pass testing.

For the second question, yes there will be quads that are manufactured under the B3 stepping. To avoid confusion when buying one, the new quads will have the 9x50 numbering system instead of the 9x00 quads that originally launched using the B2 silicon stepping. These should start to be shipped out soon starting with the 9550 and 9650 phenoms soon followed by the 9750 and 9850. Tri-cores will have the number system 8x00 or 8x50, i'm not sure on which one. I assume the dual cores will be numbered under 7x00 or 7x50 respectively to the other CPU's.

Hope that's explains it well enough (...most of it should be correct-ish)

 

2256 KiB / 4 = 564 KiB. . Should it not be [64 KiB L1 + 256 KiB L2]*4 = 1280 KiB. *It's easy being an editor*

*Can't. Resist. Urge. To. Correct* NO! TERAFLOPS! (1000th of a petaflop)

Your answer is located at the bottom of page 2. Intel thinks DDR2 = 2 channels, 2 DIMMS per channel; DDR3 = 3 channels, 3 DIMMS per channel. Anybody want to hazard a guess as to how many DIMMS a DDR4 IIMC will be able to access .

Curious that you would say that as there is a reasonable chance Larrabee will focus heavily on ray tracing. If that is the case R6xx is better equipped (I think, depends on dependency) to deal with that than G8x/G9x.


Now that my quoting is out of the way: Intel needs to work on their slides; the 'Enhanced Cache Subsystem' slide (#14) has me believing that part of the 'Enhanced Cache Subsystem' is gold. Pure functionless gold. While slide 12 has the "33% more parallelism" bubble covering the bar chart . Intel also decided to put RAS features, RDIMM and UDIMM support on one of their slides; could somebody tell me what these mean please.

Anyway enough about Nehalem, what about bulldozer?

 

32 nanometer fabrication...

320 angstrom fabrication...

It boggles my mind a little bit each time I think about it. Just how much further can they push towards a diffraction limit? What sort of distances are they having to maintain between template and substrate to achieve this (think about it, maintaining somethting like a 5nm gap between 2 surfaces during fabrication) and what frequency of radiation / source are they using? Synchatron x-rays?

I guess they will keep using imersion lithography for the 22nm chips but where then, can it go all the way down to 16nm? (a covalently bound silicone atom is about 0.11nm across)

Just wow really, the speed of R & D in this industry is a little bit frightening.

Edit: google Cheesecake, they dont have to use a synchotron source, yet, they use 193nm from an ArF excimer lazer. I guess that would be a bit future future gen still.

 

this is worth a read

http://en.wikipedia.org/wiki/Double_patterning