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Pewlius Caesar
bit-tech Staff
Join Date: Nov 2001
Location: Ascot, Berks
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Intel 45nm technology overview
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Join Date: Aug 2006
Location: Elmhurst, IL, USA
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Looks like good stuff, I sort of browsed the more informational parts, but it shows how complex our little CPUs are.
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6 screens / 1 card
Join Date: Jul 2006
Location: AB.CA
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Just speculation here but if Intel were to underclock and undervolt these then go into the mini-ITX market at a performance level at least equal to Via's best could they make it passively cooled? - I'm not expecting an answer but wondering how fast they could go with passive cooling. (I still remember a time before CPUs even had heat sinks)
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I Mod, Therefore I Own
Join Date: Feb 2002
Location: Somewhere in the south
Posts: 3,460
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Great article Tim.
Technically written whilst maintaining simplicity and remaining interesting ![]() As Tyinsar says, what kind of thermal implications is 45nm going to have for laptop chips? One can only guess lower heat and less power meaning better battery life which then brings us back nicely to the article that Brett wrote
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CAMRA ***.
Join Date: Jan 2002
Location: in meh own little world
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Sweet, I think that has to rate as one of my fav bit articles ever!
I've always had a strong interest in transistors since studying them at uni so it's good to keep up-to-date!! When do you reckon these new chips will start shipping? 2h07? |
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Stuck in the Mud
Join Date: Aug 2005
Location: Bromley, Kent
Posts: 2,552
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Are these CPUs going to have HyperThreading? The Inquirer had a story saying that they would, but we all know what the inquirer is like.
![]() I had hoped that all that HT nonsense was dead.
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KEEP IT CLEAN!
Join Date: Apr 2006
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Tim, you are quite possibly mad, making this thread at 10 past 5 this morning
Anyway, I was impressed with the new mobile idea, it would mean laptops and alike would last even longer than current core 2's Sam
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Ginger Nut
Join Date: Dec 2005
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Seeing what Intel's doing next is always interesting, it blows my mind to see just how clever Intel's techs are and how much they spend on R&D.
Looking at the die for Penryn, it looks like they'll be using the same sort of idea for the quad cores as Kentsfield, it's only a two core die. On a related topic a friend of mine was doing a presentation on Intel (more importantly, SiO2 transistors. He showed a future possible design that was pretty clever, I'll try and find the image for you if I can.
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ITS OVER 8000!
Join Date: Jan 2006
Location: Somewhere in Berks Ninja Status: Lv.69
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hold on, am I right in thnking that 45nm should have a lower TDP than 65nm..??
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Pewlius Caesar
bit-tech Staff
Join Date: Nov 2001
Location: Ascot, Berks
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Quote:
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Pewlius Caesar
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Quote:
The chips will start shipping in the second half of this year. Intel hasn't committed to a date yet (at least, they haven't given us a firm date yet). After all, the chips are still in a test phase. Quote:
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hmmmm....
Join Date: Aug 2005
Location: New Zealand
Posts: 2,885
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Wouldn't it be better if they went a little bit of AMDs way? With all that cache taking up so much room... More space for actual processing, less space for bulky cache. How much do they really need that cache?
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Pewlius Caesar
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Join Date: Nov 2001
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Quote:
The other thing that I'm interested to find out is whether we'll see the same ULV dual-core parts (hopefully with similar performance to the current ULV models) with massively lower TDPs than current models, thus improving battery life massively in notebooks. I'd love to see something like the Sony VGA-SZ3XP (or the next incarnation) with the Santa Rosa platform and 10 hours+ battery life. It's already doing 7 1/2 hours battery life with a 2.13GHz Core 2.
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Pewlius Caesar
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Quote:
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hmmmm....
Join Date: Aug 2005
Location: New Zealand
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Yes, mainly the level 2 cache that takes up about half the chip, primarily for the reason that AMD chips don't seem to need all that much cache. Looking forward to the native quad cores.
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#16 | |
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Pewlius Caesar
bit-tech Staff
Join Date: Nov 2001
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![]() The reason AMD doesn't need a lot of L2 cache is because the memory controller is on-die and thus has a much lower latency. Intel obviously doesn't have that benefit, so it hides latency with large cache. Of course, the question is whether we'll see similar scaling from 4MB to 6MB as we did with 2MB vs 4MB L2, or whether that cache is added for the sake of Moore's law - we'll have to wait until we've tested the chips for the answer to that.
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hmmmm....
Join Date: Aug 2005
Location: New Zealand
Posts: 2,885
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Ah right, forgot about the latencies from lack of a memory controller. I think that amount of cache won't benifit dual cores all that much, for the quad, I can see a larger benifit, but that is just direct scaling.
The new FET design is quite good, and they will most likey find more combinations, probably with just one or two atomic layer for the gate. Any more info on how they are planning for further shrinking the nm processes? In regard to transistor design.
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The quantum limit of reality might be scaled up because we're all holograms. Obviously. Once more we see that sufficiently advanced physics is indistinguishable from getting really stoned. From here |
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#18 |
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Et arma et verba vulnerant
Join Date: Mar 2001
Location: Portsmouth, UK
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Any word on whether they are going to start pushing up clocks again? We've been stuck on 2GHz for nearly 5 years now! I want GHz not cores
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#19 | |
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Lethargic
Join Date: May 2006
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Quote:
...and who else thinks that using enormous amounts of L2 cache on the die to boost the transistor count is cheating slightly?
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#20 |
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BSc... finally
Join Date: May 2004
Location: Vienna, Austria
Posts: 3,350
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Did I miss it or is there no hint on the socket Penryn will use?
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