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Old 27th Apr 2012, 11:50   #1
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AdvancedMicro launches first 64-bit ARM server chip

AdvancedMicro has announced the first 64-bit ARM-based 'server on a chip,' complete with full LAMP stack.

http://www.bit-tech.net/news/hardwar...bit-arm-chip/1
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Old 27th Apr 2012, 11:57   #2
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So is it AdvancedMicro or AppliedMicro ?
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Old 27th Apr 2012, 12:05   #3
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So is it AdvancedMicro or AppliedMicro ?
Bah! Applied, not Advanced. My fault - I was thinking of the AMD (which *is* Advanced Micro) story I was writing afterwards... Fixed now!
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Old 27th Apr 2012, 12:21   #4
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Is this a custom implementation of the ARMv8 architecture, or based on an ARM reference design?

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Old 27th Apr 2012, 15:02   #5
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Is this a custom implementation of the ARMv8 architecture, or based on an ARM reference design?
Every ARM chip in existence is based on an ARM reference design - it's just a question of whether it's hard macro or soft macro. In this case, it's soft macro - so yes, it's about as custom as an ARM chip gets.
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Old 27th Apr 2012, 15:38   #6
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unless there's a significant performance difference when running 64 bit ARM, i think i'd rather just use PAE. PAE in linux doesn't really have any noteworthy performance differences, but you're not limited to 4gb.
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Old 27th Apr 2012, 15:40   #7
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Originally Posted by schmidtbag View Post
unless there's a significant performance difference when running 64 bit ARM, i think i'd rather just use PAE. PAE in linux doesn't really have any noteworthy performance differences, but you're not limited to 4gb.
Existing ARM server chips - by which I mean the Cortex-A15 - don't need PAE, 'cos they use 48-bit memory addressing (despite still being 32-bit chips.) Each chip supports up to 1TB.
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Old 27th Apr 2012, 17:03   #8
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Let's be clear here: this is an announcement of a working FPGA, not a working chip. But is great to see that the 64-bit ecosystem can now begin the work to get ready for real silicon when it DOES become available. Make no mistake: ARM is coming to the datacenter, and there are indeed plenty of 32 bit applications and workloads (ever hear of Java?) that will start the move 1st (with help from Calxeda!)

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Old 27th Apr 2012, 23:04   #9
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Gareth, I have to admit I just love the way you make hardware virtualisation extensions and heavy integer mathematics sound refreshing and interesting!
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Old 27th Apr 2012, 23:38   #10
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ARM on a server seems like throwing rocks at a tank. If your hardware and processing demands are that low you would be better served by virtualizing it on an existing machine and save the cost of expensive proprietary ARM servers.
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Old 28th Apr 2012, 00:10   #11
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Gareth, I have to admit I just love the way you make hardware virtualisation extensions and heavy integer mathematics sound refreshing and interesting!
I'm going to choose to assume you meant that seriously.
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ARM on a server seems like throwing rocks at a tank. If your hardware and processing demands are that low you would be better served by virtualizing it on an existing machine and save the cost of expensive proprietary ARM servers.
You're missing the point: the servers these are aimed at do lots of small tasks at the same time; in the power envelope of 16 x86 cores, you can get 512 ARM cores - and thus run 498 more threads. (Numbers pulled from you-know-where for illustration.) Doesn't matter how much you virtualise, if you've got sixteen cores then you're only running sixteen threads simultaneously (modulo tricks like Hyper Threading.)
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Old 28th Apr 2012, 10:47   #12
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I'm going to choose to assume you meant that seriously. You're missing the point: the servers these are aimed at do lots of small tasks at the same time; in the power envelope of 16 x86 cores, you can get 512 ARM cores - and thus run 498 more threads. (Numbers pulled from you-know-where for illustration.) Doesn't matter how much you virtualise, if you've got sixteen cores then you're only running sixteen threads simultaneously (modulo tricks like Hyper Threading.)
Yes, and an ARM server like this with (relatively) low performance per core but a high core count makes it especially suitable for tasks that are easy to parallelize but simple to compute such as a web server. Each individual request is straightforward to handle, but handling 500 of them at a time is a lot easier on 500 cores than time-slicing them across 16 cores.

For computationally intensive work, Xeons obviously still remain the best choice.
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Old 28th Apr 2012, 11:51   #13
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Quote:
Originally Posted by Gareth Halfacree View Post
Every ARM chip in existence is based on an ARM reference design - it's just a question of whether it's hard macro or soft macro. In this case, it's soft macro - so yes, it's about as custom as an ARM chip gets.
No, there's three ways of licensing: hard macro (the customer gets a silicon layout that they can send to a foundry), RTL (the customer gets source code they can plug into their own cell libraries and turn into a hard implementation themselves, what you call "soft macro") and architecture license (eg Qualcomm make their own CPUs from the ground up, just using the ARM instruction sets). So to answer r3loaded's question, yes, this is probably a custom implementation, not derived from a reference design.

Quote:
Originally Posted by Gareth Halfacree View Post
Existing ARM server chips - by which I mean the Cortex-A15 - don't need PAE, 'cos they use 48-bit memory addressing (despite still being 32-bit chips.) Each chip supports up to 1TB.
LPAE is 48-bit physical addressing.
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Old 28th Apr 2012, 19:38   #14
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No, there's three ways of licensing: hard macro (the customer gets a silicon layout that they can send to a foundry), RTL (the customer gets source code they can plug into their own cell libraries and turn into a hard implementation themselves, what you call "soft macro") and architecture license (eg Qualcomm make their own CPUs from the ground up, just using the ARM instruction sets). So to answer r3loaded's question, yes, this is probably a custom implementation, not derived from a reference design..
You're quite right - for some reason I completely forgot about architecture licensing.
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