News AMD sneaks strained silicon into chips

Earlier this week, AMD announced that they had begun shipping 90nm parts for revenue. It's now reported that these 90nm processors are going to make use of strained silicon.

Advanced Micro Devices has begun to incorporate a form of strained silicon into its chips, a design twist that will let the company increase the performance of its processors.

The strained silicon is being incorporated into all of AMD's 90-nanometer chips, which the Sunnyvale, Calif.-based company has just started shipping to PC makers. The technology also will be added to 130-nanometer chips that will be released this quarter, an AMD representative said Thursday. (The nanometer dimensions refer to average feature size on the chips. A nanometer is a billionth of a meter.)

Strained silicon is a design technique in which silicon atoms are forcibly pulled apart from each other. With the atoms spaced out further from one other, electrons can move more rapidly, similar to how a hockey puck can zip faster across a rink than across a frozen lake. Faster electrons lead to better performance.

AMD's use of the technology in the chips was first reported by The Semiconductor Reporter.

Although AMD is not divulging many details about its strained silicon, the company's technology differs from the way IBM and Intel incorporate it, the AMD representative said. Both IBM and Intel embed a layer of silicon and larger germanium atoms into chips. This stretches the silicon atoms that sit above that layer.

It will be interesting to see what, if any, performance gains there are from the use of strained silicon.

Full story on CNET

 

Do you think this will result in better overclocking??

Death

 

possibly... but it could also have a negative effect on the use of high voltages. Electrons are going to be travelling faster and thus when voltage is increased, electron tunnelling is more likely to occur. Only time will tell I guess... wait for someone over on XtremeSystems to kill one from too much voltage

 

The other adverse effect is going to be extra heat. The now infamus prescott chips have that same problem with the same 90nm cores. BUt times must change. Remember the days when your cpu didnt even need a heatsink? now we are up to watercooling and things will continue to get hotter. Pretty soon we are going to have to throw away home heating and jusp place a cuple of pc's in each room and just run a loop of super pi.

 

That's cause the prescotts leak though. Yea, days when cpus didnt need heatsinks was the days when you could have a few dozen transistors in a chip running at a few mhz. Not hundreds of millions running at thousands of mhz.

 

The reason that presscotts leak through is because of their smaller fabrication process. It becomes harder and harder to keep the electrons on path when the size of the path deminishes and is still expected to carry more signal. therefore they lower the voltage on the chip but increse the wattage.

Also another reason for presscotts heat is the aded pipeline length. If the pipeline was shorter the chip would be more efficient but way less scalable.

 

Yea, do the same and more in a smaller space. Whereas the old chips didnt have to worry about this cause they were built on .5/.35/.25micron etc that was my point.

Of course - if you only had 10 stages it would do more IPC, but then you wouldnt get jubblies like SSE3 etc. If they found a way to bypass all the crap for code that doesnt use it it would be better.