Hardware How to Make a CPU: From Sand to Shelf

Remember the bridge mod with a pencil ? That was awesome

 

Really really interesting article.

I presume Intel provided the pictures?

And +1 for finding out how cache integrates into the CPU, is it just more transistors?

 

Good article

Maybe you could have explained with more detail the final process of packaging, each time the companies start producing processors, they are all aimed at the hightest speed, and its conditions like resistance to heat and purity of the material wich affects the different results.

they are tested with different voltage until they start being unstable, at this point they're tagged with the closest frequency they were stable.

What this means its that a processor tagged 2.5 ghz could be 2.51334 or 2.498845 in reality, every processor have different frequencies with others, no mather if they're tagged as 4 Ghz or 5 Ghz, and this is also why some processors overclock better than others from the same line.

Im sorry but I was curious about the factory process a few years back, and when i found out this about the frequencies i thought it is the most amazing thing of the process, never saw that comming.

cheers

 

I think the main reason its the quemical reaction X-ray wotn produces on the surface of the metal, the wafles react chemically with the UV producing conuctive or non-conductive material for the transistor

X-ray would just cut the hell out of the silicon.

 

Awesome write-up, and I loved the renders!

 

They've used (or still use) x-ray lithography before on chips to great effect, so why not in this instance? There seems to be no real reason no to. Veeery strange!

 

@Azayles: Have they? As I recall, the wavelength of light used is 193nm. X-rays are a good deal less, 10^-9 to 10^-11m. At present, the industry is looking at (finally) moving to 'extreme UV.' I thought the wavelength of light used stopped following the process node down several years ago, at about 90nm, and the main effort now is to overcome the diffraction and other optical effects that occur.

 

why wouldn't it be?

it's just more static memory. http://en.wikipedia.org/wiki/Static_random_access_memory

only reason it looks funky on die shots is because it's so uniform compared to other parts such as the ALU.

 

They have yeah, though it's very likely what you say about the wavelength limitations of light not being met yet means there's no real call for x-ray lithography. At least for the time being.

 

I would assume that this is because of secondary / auger electrons being emitted and causing damage to the resist and pattern. I bet this would push the failure rate way up.

Also to consider is the gap between resist surface and aperture, aperture diameter being S then the gap needs to be maintained at S^2/3*wavelength. So for 1 nm x-rays you are looking at maintaining a very narrow gap over a large area at significant throughput speeds.

(Im guessing that initial equipment costs for the synchrotron(s) would be negligible in the scheme of things?)

Really though its all about the relatively high energy of those x-rays, and the fact that in double patterning they have an effective route to 22nm via UV Lithography.

 

Yup cache is no different in that it uses transistors in the same way, it differs in other ways though, years ago I did an 8T(transistor) dual port SRAM, can't remember if it was 90nm or 130nm now (almost 10yrs ago), the area of the bitcell was something like 1.2um sq, took a couple of months to develop due to having the ability break all the usual design rules due to uniformity/pattern density of an SRAM and the knowledge from process guys via numerous test vehicles on what risks you can take, compared to normal analog or digital standard cell layout it was a bit finger in the air voodoo stuff, i'd look a the layout and think that would never work but it always did. (with the aid of some redundancy )

 

Now I really want to go to a CPU manufacturers plant and watch them get made. The interconnect machine has got to be a wonder to see - laying millions of little copper bars up to 30 high? It just makes me geek out....

Very enlightening article. It makes me appreciate the humble CPU even more! And whats hilarious is that I can own a chip consisting of millions of transistors for just pennies... i7's pushing over a billion now is just amazing....

 

Thanks for the positive comments on the article guys.

For those of you who asked yes the pictures were provided by Intel, so you may have seen them elsewhere used for other articles.

 

One thing I didnt see was the time it takes to make a chip. And what is the yield on most wafers? This has intrigued me... lol

 

Wow, one of the best articles on Bit-Tech yet! This is something I have wanted to know for a while now but tbh I haven't been arsed to research it. Now I can refer to this. Seriously, kudos for another great technical write up BT!

Yeah I always wondered what the reasoning for that was too.

 

If you want to know more about lithography watch these 2 excellent lectures from nptelhrd on youtube (Indian Institute of Technology in this instance) Tons of other crazy vids on their channel too

http://www.youtube.com/watch?v=v9eGO5OjC8A

http://www.youtube.com/watch?v=pcAEEw2Gadg

 

This is correct, its implementation was slightly different though and the article covers Intel's 32nm implementation of the material, hence my choice of words.

Apologies if the sentence was misleading, I've tidied it up now.

 

Very interesting.

 

And now that you practically got a how-to: Who fancies some DIY action?

 

Search for the Czochralski process on wikipedia, its how they grow high-purity crystals to begin with. it invloves rotating a seed crystal the opposite direction to the rotating crucible that the silicon solution is held in. The seed crystal is drawn VERY slowly from the melt creating a cylindrical ingot which is cut by a diamond edged saw into wafers. The rotation and hence, shape, is essential to creating high-purity electronic grade silicon. What isnt mentioned is that there is a further purification technique called "zone refining" in which the crystal is pulled through a heater, focusing on a small part of the ingot at a time, drawing any impurities to one end called teh "Tang end" which is then disposed of.

As for production waste? Its not as much as you may think, for most companies and most IC's produced in the world, you can nearly use an entire wafer due to the small die footprint. Its only companies like intel which make extremely complex, large dies, where waste comes in. Infact thats why intel are looking to move for a 450mm waver size compared to the 300mm thats used now, they reckon due to the size of the IC's thre would be less waste per unit volume.

No, its not like that; though thats how the article makes it sound. A single machine doesnt lay all the interconnecting tracks like point to point wiring, they're made with the same process as the transistors themselves, a layer of copper or aluminium in some processes is deposited across a section of the wafer blaketing it, between mask layers. Areas are removed with a chemical wash or ablation leaving the conductor material only in the sections we want it creating the interconnect between individual transistors. That layer is sealed off, usually with silicon dioxide or the high-k insulator depending on how close the tracks are (parasitic capacitance and quantum tunneling between tracks is a MASSIVE problem the smaller you go, which is why we need high performance insulators like the high-k stuff intel use, another reason is restricting dopant diffusion but thats another story) and the second layer is added above if more connects are needed. Its kinda like photoshop? You can add layers to a photo, it might be a boarder and another layer might be a lighting effect. You take all the layers together and that creates the picture? Same with interconnects, the entire chip is made from layers stacked on top of the one below creating teh finished product.