Hardware How to Make a CPU: From Sand to Shelf

I'd LOVE to have a complete edged wafer framed on my wall. Wonder where I could get a scrap wafer? Approach Intel?

 

I'd bet you can get them off ebay

 

Holy cr@p that's amazing, thank you!
I looked on ebay.co.uk 'cause I'm from the UK, but I'll set up an account on .com tomorrow and bid on that

Edit: My post made no sense I'll make a new account on .co.uk and just list the international sellers so I can see the product you listed.
He has more! They're wonderful!

 

How big a wafer are you looking for? The standard industry 300mm? Cos we have some 80mm ones in the lab at uni. And would you like it patterened? Standard wafers are just highly polished mirrors before the designs are added.

 

That'd be fantastic How much would it cost? I'm in the UK, England. Patterned would be ideal.

 

Excellent article. Well done!

 

Very cool article.

 

which uni are you at, may i ask?

a wafer is probably the geekest thing you can have there should be gift shops for this kind of stuff, makes you wonder why Science museum in London doesn't have it.

wafers are relatively cheap, most cost are from R&D of that particular product. FPGA, that's where it's at, i was playing around with a roughly £2000 Xilinx Virtex late last year, and a £1000 demo unit of Altera Stratix a year ago. you can actually do stuff on those, just need a computer and a USB to the FPGA bard.

 

The cost would be minimal if I can get hold of one, we usually use them to show second year undergrads how IC construction works, from the wafers right through to packaging including how the doping, etching and masking processing works. The circuit we have the masks for is pretty basic and once we make them we either bin them or give a few samples to the students as a souvenir, so if I can get hold of one i'll give it to you for the cost of postage. I'll let ya know.

Manchester, graduated there a few years back but a Ph.D oppertunity came up in the materials and nanostructures group the guy running it was my undergrad tutor we got on well and I couldnt say no

 

For those interested the TV show How do they Do it went to Texas Instruments fabrication and explained it well.

Oh and about the circular saw cutting, they actually use a piece of wire connected to a band saw like machine.
It's so thin it means they save material as opposed to cutting it out.

Also, the silicon ingots are so strong they are entirely suspended from a single strand before cutting.

 

Heres the actual video from Intel, its called From Sand to Silicon:

http://www.youtube.com/watch?v=Q5paWn7bFg4

 

If you ever pop down to the metallurgy and materials dept at birmingham they have display cases of 300mm Si disks with chips on, as well as some ingots and associated parephenalia

 

very nice, Article thanks

enjoyed reading this

 

You'd probably need a telescope or uber microscope to see it building anything in the process. I'm pretty sure adding SEM equipment in the middle of building the bars is a recipe for disaster.

 

Very nicely put, and correct for upto 2 maybe 3 layers.

Anything above that uses the "Damascene" process.
It's the other way around, as shown in this article actually.
First you get a layer of silicon dioxid, in which you etch pathways, think trenches. Everything is covered in copper, then you polish back till silicondioxide with copperfilled trenches. Those are your "wires".
The polishing ensures you have the planarity to repeat this stem multiple times.

Weeellll, I used to ...now I'm just making silicon wafers

 

One question I have that I always assumed I knew was what determines you process node size, I always assumed it was min gate length related but one 40nm process I worked on was drawn at 45nm, optically shrunk to 40nm but the gates of the standard cells after shrink were 36nm, so why would you call it a 40nm?

 

Ah that sounds pretty cool! If you walk around the D floor in the sackville street building at manchetser (it used to be part of UMIST) we have one or two displays on the wall, one of those has a 300mm wafer but unless you know its there you'd never know. It'd be nice if we could put it all in one room and show it off to any prospective students, but the uni doesnt seem to care

 

Great article guys. Encore!

 

I always thought the feature size was the average of the width, and the space, in between metal interconnects connecting bit cells in a DRAM if one were to implement a DRAM using this process. I think in real terms it's supposed to be a vauge indicator to the average feature size, so that all manufactures can agree on a terminology standard. And not a definative specification that states the transistor chanel length MUST be 45nm under pain of death!

Check this link out for some info:
http://vlsicad.ucsd.edu/~abk/TALKS/michigan-020304.ppt

 

That'd be fabulous if you could Thank you again :-D