News Intel CEO blames aggression for 10nm missteps

Trace width is now well below 30nm for the lowermost metal layers. That's the pitch for those layers (distance between centres of adjacent traces), but the actual traces are much narrower - down to the 10nm range - due to both the multiple liner layers, and the geometry requirements of SADP & SAQP that limit relative feature scaling (that Self Aligned bit is key). With 2 laydowns between each trace (liner & barrier on each side) a 2nm liner thickness contributes 8nm to the total pitch before you even start adding the metal itself, even if you butted the traces right up next to each other without any routing!

Why do you keep bringing up trace resistance only to then immedaiately dismiss it as not a problem? It's not the problem that Co is intended to solve in the first place (Co has a higher resistance per unit area than Cu, after all).
Besides, that link is talking about the contact layer, not the metal routing layers. Please flick back up to the link I posted earlier that describes the metal layer issue.

 

Again where are you getting this from as we know TSMC's Minimum Metal Pitch is 40nm and that's on their 7nm node.

Because it seems you're not reading what I've typed..."some 'study' sort of showed that copper interconnects became a problem under a certain size but the theory didn't stand up when put to the test"

As it seems to have alluded you allow me to explain, Applied Materials produced a study shortly after buying a couple of semiconductor equipment company that just happened to be developing equipment involved in cobalt disposition, that study claim something like this would happen to the resistance as line width shrunk....



And so everyone would have to buy their sputtering equipment because cobalt was the best solution, with me so far?

What's been discovered, as I've repeatedly said, is that the increased resistance does not become a problem until line width is much lower than AM claimed, AM basically exaggerated by claiming resistance started to become unmanageable between 40-30nm, probably because they didn't want to wait until the BEOL was under 10nm where it does actually become a problem.

Perhaps you need to re-read that link you posted earlier yourself as it seems you've conflated the MOL with the BEOL.

 

I know, they lost me days ago and even though I have re-read their posts twice, I still don't have an effin clue what they are arguing talking about.

 

Sorry, I'll stop after this.

Basically edzieba is saying what's caused Intel so many problems with their 10nm node is the equivalent of not having enough room to run a load of cables because the wires along with the insulating materiel around each wire takes up too much space, a bit like trying to squash loads of cables into a cable tidy on the back of your desk.

Whereas I'm saying it's not that there's not enough room to lay your cables it's that the cables are to thick because someone over estimated the gauge.

 

Trace pitch != trace width, the the same reason cable thickness != conductor dfiameter.

And as I've been stating since the start, the trace resistance is a total red herring (you were the only one to bring it up in the first place!). The problem is not resistance of the traces, but width of the required liners. Note even in that diagram you posted that while the trace width reduced, the liners remained the same width? That's the problem limiting minimum pitch!

 

So if the liners are the problem make the traces/wires 1 atom thin and the liner 1 atom thin....problem solved...oh no wait, you can't do that because thin wires have more resistance than thick wires so you wouldn't be able to get any usable current out of the other end.

 

This right here is the issue: the liner is already at the minimum thickness to be of utility as a diffusion barrier. Regardless of trace width, the liner isn't going to be getting any thinner.

 

I guess you missed the reductio ad absurdum i was using to make a point.

Also it would be nice if you'd bother to answer some of the questions i asked, like where you got the idea that "Trace width is now well below 30nm for the lowermost metal layers" and where you got the idea that the DB what's preventing them from using Cu, if you've conflated the BEOL and MOL.

I mean even the link you posted earlier in an attempt to prove the DB was the problem tells you Intel's 10nm BEOL MMP is anything from 36-160nm.

And it tells you...

But apparently the trace resistance is a total red herring.

 

The problem is that inability to reducto is the entire problem in the first place.

Simple mathematics: take a line pitch of 36nm. Each Cu trace needs a barrier and a liner layer, and both have bottomed out at 1.5nm-2nm minimum effective thicknesses, for a total of 4-5nm per side of each trace, or 8-10nm of the centre-to-centre distance being taken up by lining layers. For a 36nm pitch, that gives a trace width of 28-32nm at an absolute maximum, and ignores that traces do not simply butt right up to each other but require space between them due to the requirements of mask patterning, and that physical deposition also limits minimum valley width (because narrow enough valleys cause problems with self-blocking of particles resulting in voids in the side walls). Practical Cu trace widths are on the order of 20nm give or take (will vary depending on local geometry, straight runs will be thinner than corners, again due to mask patterning requirements).
M0 and M1 are literally right at the front of BEOL, they define the interface between FEOL and BEOL (FEOL stops where M0 starts). You need to go many layers up through metalisation before you can start calling it MOL, and at that point the traces are wide enough that everyone will continue using Cu for the forseeable future.

I've also yet to find anything to refute the basic resistance scaling of Copper (or any other metal), as trace widths reduce resistance increases is fairly basic physics. Even TSMC have already swapped in Cobalt for the contact layer (immediately below M0) for 7nm, and that's only going to migrate up the stack as they want to pack transistors closer and closer together.

 

I give up, when the article you linked to yourself says you're wrong but you keep insisting that you're not there's really no hope.

I mean first you say resistance is a red herring and then you agree with me by saying as trace widths reduce resistance increases is fairly basic physics, one moment you're saying resistance doesn't matter and now you're saying it does.

 

It's too hot to even start to try and understand what's going on here.

 

Resistance is a red herring because regardless of whether the increase in trace resistance is a problem in practice or not*, the lack of reduction in liner thickness is a problem as that does not shrink with trace width.


* And I've yet to see any article claiming that trace resistance does not increase as trace width decreases.

 

Basically this.

 

With a side order of this: