It's not really a physical HT. It has 2 complete cores and 2 complete FPUs/ALUs and separate caches. Only the memory bus is shared where everything is shared under HT. It's just a dual processor mobo on a single chip, but like said before only multiple thread processing will benefit - like any dually setup. But it's not instructions, it's data. :/ The EEs are L3 which the core's werent specifically designed to address, and, yes the performance benefit of increasing the cache is diminishing gains but L2 will be still be used, although i do see your point about "doing enough to fill it" but i think it's todo with the processor's "cache engine" (if there is such a thing) rather than software designed to use it. If i could find a program to test cache useage id give it a go. Too true. It's why Celerons still sell.
