Low vol 10nm products this year (read: maybe one you can buy, in maybe some limited regions) "2019" for 10nm volume production, so many are reading that as second half of the year Whiskey Lake will be another 14nm Skylake variant between now and then. That's the FIFTH 14nm product and FOURTH Skylake arch 8 core LGA115x product(s) leaked in docs Z390 and X399 leaked in docs Cascade Lake server chips coming later this year, but X399 supposedly still Skylake-X again Jim Keller (ex-AMD, ex-Apple, ex-Tesla) has gone to Intel TSMC is already shipping 7nm products. Will have 7+ on EUV before Intel is shipping volume 10 without. TSMC will be ~12-18 months ahead of Intel with EUV. Samsung very soon shipping first 7nm parts GloFo will have 7nm low volume 2H18, volume next year: Zen 2 @ 7 will likely be ahead of Ice Lake on 10+.
See also here, this morning. Whiskey Lake wasn't announced as part of the delay; it's been public knowledge since late last year. See also here, also this morning.
Sorry if my brevity made me seem snippy - I was juggling a dozen things at the time. I merely meant to add more detail!
The interesting part for me is why their having problems, from what i read random flaws keep cropping up and trying to find where the flaw is and in turn why the EUV process caused it is proving to be really difficult at that scale, Semiconductor engineering had what i found an interesting article on it here.
mean while AMD are on track for 10nm and will beat intel too it. Im sticking to x58 till DDR5 is out, skipping DDR4 as its coming to the end of its life now. Looks like ill be getting my first AMD cpu with DDR5 2019! hope it will have the same life span as my x58 did, stuck with it for 10 years next year and is still great for gaming.
'AMD' aren't on track for anything, they sold off their fabs almost a decade ago to form Global Foundries. GloFo, TSMC and Samsung are also struggling with getting new process into volume for larger chips. Most have given up yet again on EUV and billing their next gen process as 'EUV ready (but we'll keep DUV multipatterning for now)'. TSMC appear to be closest to shipping, but for smaller mobile dies. GlobalFoundries 7nm: samples 'soon', no word on volume. TSMC 7nm: Claim to be ramping up volume production, but their first customer appears to be Apple for A12 SoCs, which may mean nothing for anybody else for a few months as Apple consumes all volume. Samsung 7nm: Not starting until later this year. Supposedly Samsung are trying to buy up ASML's output of EUV machinery to prevent TSMC ramping up. Samsung 8nm: was 'ready for production; at the end of last year, but appears to not have actually produced anything. Intel 10nm: Ongoing yield issues, likely due to using a smaller BEOL pitch than others.
It's well known Amd have a joint venture with multiple fabs to build there chips which is fine by me. And they have reported no set backs at all. I'll get the quotes when I'm not at work but they will beat Intel to 10nm. We are talking 10nm here not 7
And AMD do not work on the actual process technology any more. They implement designs based on the capability of processes developed by others, but so do many other companies (e.g. Nvidia).
EUV just feels doomed to fail, current technology is not ready for it. The unpredictable failure rates will surely prevent it ever been successful. If Intel and all there cash can not make it work I doubt anyone else can either. Tsmc will surely sell whatever Apple wants first and everyone else is a distant second in that one. People expecting special leaps from 14 to 10 can’t really see it. For most consumers a current chip will last them 10 years +.
EUV is already being used to better effect than quad patterning, but only test and limited runs not mass production. It's the only way forward. The limitation is that its much more power hungry and much slower making it uneconomical, but both those things are being rapidly improved. Quad patterning is very slow and complex also: it's required for 10 and 7 at TSMC. 12 is the lowest you can get without it iirc. They're at an inflection point of economics. Intel is margin sensitive and it's foundry business is ****ed so it can't rapidly move to EUV, but foundries will implement whatever providing someone will pay for it, that's why TSMC and Samsung are pushing ahead. There are decent gains for big generational jumps: 28/22/20-16/14/12-10/7
Other way around: Intel's 10 to TSMC's/GloFo's 7. So TSMC is 12 months ahead of Intel, and 12-18 months ahead on EUV
Ahh yes sorry. Also What’s the source on them being roughly the same. I’ve seen it multiple places but don’t know where it started
You've got most of the tech press placing TSMC 7nm as smaller than Intel 10nm using transistor gate pitch, and the silicon press placing Intel 10nm as smaller than TSMC 7nm using metal pitch. Until both processes have comparable (i.e. not a low power SoC vs. a large die) dies fabbed and available for dissection (and for practical perf/watt testing), there isn't really going to be a reliable way to say "X is better than Y!". 7nm/10nm can go either QMP or EUV at roughly the same huge cost. Which makes the better bet depends on what happens beyond 7nm/10nm: If everyone sticks with Silicon and goes for "make smaller fins for finFETs" than EUV is necessary. If new 3D geometries are necessary to advance (e.g. GAA, tunnelFETs, nanowires, directed-self-asembly, etc) with only minor substrate changes (e.g. SiGe) then multipatterning is going to be needed to create those anyway; it makes sense to work on the hard multipatterning problem on DUV and let everyone else beta-test first-gen EUV than adopt early EUV then try and figure out multipatterning while also troubleshooting EUV at the bleeding edge. If Silicon finally hits a wall and a move is needed to another substrate (e.g. direct deposition onto Graphene, or Indium Antimonide), or to different transistor types (e.g. Spintronics) then Silicon EUV process machinery may end up needing to be replaced anyway and the whole thing is moot.
Remember the days when the quoted node size was the size of the smallest feature? Pepperidge Farm remembers.
Yea I agree there's little-to-no value in the numbers going forwards. It's the generational upgrades that are most significant, not the half or even 2/3 nodes that Samsung is quoting. TSMC can do quad patterning with DUV though - it did that for 10nm and first gen 7nm. It's an expensive ******* that takes longer than many order cycles, so unless you're charging super premium $ and have an absolutely assured product it's not worth it. So all this leading edge process is really going to affect entry/mainstream, possibly even mid-range parts in future.
That's why TSMC (and likely others) are keeping around an FD-SOI process for everyone who doesn't want to pay the massive costs for 7nm. That day died when the Gate Oxide hit ~1nm and the hard leakage wall (not coincidentally the same time processor voltages stabilised ~1V, and clock speeds started to stabilise between 4GHz and 5GHz), around 2005.
