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News PCI-SIG announces 64GT/s PCI Express 6.0

Discussion in 'Article Discussion' started by bit-tech, 19 Jun 2019.

  1. bit-tech

    bit-tech Supreme Overlord Staff Administrator

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    Read more
     
  2. Jeff Hine

    Jeff Hine Nothing special

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    5x2 = 8...? Really...?
     
  3. Gareth Halfacree

    Gareth Halfacree WIIGII! Staff Administrator Super Moderator Moderator

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    My bad: it's 'cos I'd originally started writing it in megabytes per second (which was a very-almost-doubling from 500MB/s to 985MB/s between PCIe 2.0 and 3.0) but switched to gigatransfers per second. Fixed now!
     
  4. adidan

    adidan Avatar now in stock for xmas 2019

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    Don't pick on @Gareth Halfacree he's obviously just been doing his accounts for the taxman.
     
    MLyons and Gareth Halfacree like this.
  5. Jeff Hine

    Jeff Hine Nothing special

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    Joking aside, I read the article 'literally' and it didn't make sense :p
     
  6. mi1ez

    mi1ez Active Member

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    USB-IF could learn some lessons from this...
     
  7. Corky42

    Corky42 Where's walle?

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    So something i don't get and I'm probably going to sound stupid for asking, but from what i gather implementing PCIe 4.0 on X570 has been more involved due to difficulties in maintaining signal integrity between the CPU and first PCIe slot, isn't that only going to get worse with PCIe 5.0/6.0?

    Or is that what the four-level pulse amplitude modulation, that i don't have the first clue about, intended to address.
     
  8. Anfield

    Anfield Well-Known Member

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    If what AsRock told GamersNexus is accurate, then yes, implementing PCIe 4 is a pain in the lower back (and also a major factor in the much higher price of X570 boards), so yep logic dicateates that implementing PCIe 5 & 6 will be bloody hard too.

    No clue though how much stuff like four-level pulse amplitude modulation can offset that difficulty.
     
  9. edzieba

    edzieba Virtual Realist

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    PCIe 4 doubled signal rate compared to PCIe 3.0 (implementation headaches), and PCIe 5.0 doubles signal rate again (more implementation headaches). PCIe 6.0 does not, it avoids signal rate increases by changing signal levelling. That's somewhat less of a headache as it does not change the traces, 'just' the PHY layers in the chips.
     
  10. Anfield

    Anfield Well-Known Member

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    Sounds like a good reason to just skip PCIe 5 then:thumb:
     
  11. edzieba

    edzieba Virtual Realist

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    Depends on who you are: if you're making a motherboard, implementing PCIe 5.0 means you're already ready for PCIe 6.0. If you're a chipmaker (at either end of the bus), implementing PCIe 6.0 means you have to deal with both the PCI2 5.0 signalling rate increase and the switch to 4-level PAM.
     
  12. play_boy_2000

    play_boy_2000 It was funny when I was 12

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    Is it just my imagination or are we going backwards now by adding faster links that draw more power and are harder to implement, yet almost nobody uses.


    I was about to mock the pointlessness of USB 3.2 10/20gbit when it occurred to me that M.2 NVMe drive prices have tanked and external enclosures are a thing. Dammit, there goes another $97 (58 quid) on Amazon; up to 900MB/s on a thumb(ish) drive should be fun though.
     
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