Discussion in 'Article Discussion' started by bit-tech, 18 Oct 2018.
typo in the penultimate paragraph...
"....At the asme time...."
I'm hoping you meant "Acme" but I'm fairly sure you meant "same"....
Be interesting to understand how Samsung have achieved it, while Intel haven't... I suppose all that's top secret industrial stuff though...?
Basically there are two parts to it:
With Samsung and TSMC the whole 14 / 12 / 10 / 7nm thing is little more than marketing names for general improvements in manufacturing these days unlike Intel which is still trying to hold itself to at least some standards in that regards, but even they have to fudge the numbers a bit to get to 14nm.
The other factor is the complexity and quality requirements for the chips, a monolithic 28 core server CPU is not only harder to make than some minor chip, but also has to meet far higher quality standards than some smartphone SoC, RAM chip etc.
I was thinking about if I should upgrade from 16GB to 32GB but it seems I should wait for DDR5. 16Gb DDR5 memory is expected to start at 4800MT/s expected in a year. together with the new tech from Samsung we should see some nice kits. I'm hoping my next build will be DDR5 PCIe 4.0.
That is a very optimistic schedule, not even talking about the RAM itself, but about what CPU would support it.
Intel is scheduled to bring a shrink at the end of 2019, so unless they take the extreme risk of also rolling out at new arch simultaneously with the shrink then they won't support DDR5 before 2020 and AMD has committed to AM4 up to and including 2020, so on the AMD side DDR5 won't hit before 2021.
The layout complexity goes up exponentially regardless of design complexity, nothing is simple any more, my first sub 7nm layout of an inverter which should be very simple had a few thousand design rule violations gone are the days of slapping any old **** down ( by that I mean being a creative full custom analog layout artist ) .
With SOCs it can be a lot easier as you have a standard cell library to pull from and automated tools to do the work, full custom analog is the time consuming challenge, so much so it has become very digital like in its structure.
Ah, back when "taping out" meant literally taping out...
Intel (and TSMC) have decided to wait until someone else takes the EUV-in-production bullet to work out all the bugs, and instead are sticking with multipatterning.
With the lack of EUV pellicles, this probably won't be a process advertised for 3rd party parts (or if it is, at some exorbitant cost) as it'll eat through masks. It's also an 'at least one exposure' EUV process rather than an all-EUV process, so technically Samsung could be using EUV to expose some extra wide BEOL step and use multipatterning for the fine pitch FEOL stuff, and still claim "first production EUV LOL". It'd be pretty will and they'd be rumbled as soon as someone decapped a die and saw the telltale SAQP artefacts, but it would technically not be lying.
It's a widely believed fact that the 10nm/7nm delay is due to lack of availability of sufficiently fine tape...
Ah.. the old "cant find a fine enough tape" excuse.
tha'ts not really what's holding Intel back. I think that, in essence, they just spend so much time and money, effort and man power, on trying to outdo AMD, instead of racing in their own race, that they've missed the really fine tape that is stored at the back of the stationery cupboard.
Samsung is a very different beast to Intel though. It's a hugely different business model, more akin to Google or Amazon in the sheer audacity of scale of items that they sell/provide. Imagine Intel having a new chip launched and the next day a new fridge.. and then a new dishwasher..then a mobile phone range....then headphones... then a blueray player...and TV....then helping in designing shipping and heavy indusry.. all with their name on it.
I mean... those don't all come from the same company. They have the same logo on them, I'll grant you, but the people running the foundries aren't the people building the fridges. Likewise, the people making Yamaha pianos aren't the people making Yamaha motorbikes...
What you mean they don't just change the etching process at the foundry to produce a motorbike, and use a bigger laser to imprint the logo, awww ruined it for me, next you'll be telling me there is no Santa
TSMC announced their EUV less than a week ago (up to 4 non critical layers only though), so it will be funny to see which one of them goes with the "first production EUV LOL" claims.
I believe the Intel delays are also due to trying to have a (* be warned this is where my knowledge starts to go) smaller pitch in the CPU. They were aiming too high and trying to squeeze out too much extra perf if what I gathered from the docs I've read are correct.
i do know that... but you know that I knew it, right? I hope you did....
but my badly worded point was..... IF Intel chose to stop trying to beating up their opposition at every turn, and just got on with being a good company making good products, I think they'd impress more. Beating the opposition can be done without making yourself look like a dick.
If Intel had spent a lot of their time and effort on making.. let say.... a really good Microwave Oven, that was world class.. and less time arsing around with "we're better than AMD, lets prove it with hidden air con units and wrongly worded PR info .. they might be richer AND we'd all be better off.
Samsung have, to a certain extent, done that. They've chosen to take lots of markets and be good in them all.
So.. the question you should ask yourself is this: have Samsung regularly spent all their efforts on trying to bad mouth Philips and LG and Bosch and Zanussi?
Even once you get you hands on some really small rolls of tape you can't finding the start, you end up picking at it for days.
I knew you knew, and I think I know you knew I knew you knew. Or something. Look, I may have gotten into the whisky a little early today, OK?
god I wish I had.... just an excess of Caffeine here
GloFo decided the hardest scaling problem would be EUV, and decided to tackle that first. Turned out that was too hard, so they dropped 7nm entirely
Intel decided the hardest scaling problem would be switching from Copper metal layers to Cobalt layers. Turned out this was pretty danged hard, so while they've been fabbing chips at scale for the last 4/5 years, they haven't gotten yields up to scratch.
TSMC decided the hardest scaling problem would be EUV, and decided to tackle that first. Then when EUV turned out to be pretty hard, they decided to just go with it and see how small they could scale conventionally and move parts to EUV eventually at some point maybe.
Samsung Initially decided to just go with it and not tackle anything for 7LPE on DUV, then quietly dropped 7LPE entirely and produced 8LPP (close to identical dimensions to their 10nm process) to focus on 7LPP with EUV as their 'second gen' 7nm process (ignoring that the 'first gen' process was never actually used by anyone to make anything). Interestingly 7LPP is using almost identical design rules to 8LPP (and rumour is that the silicon layers themselves are still DUV SAQP and basically the same as 8LPP).
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