News TSMC announces 5nm, 3nm fab plan

oooo 3nm node -sexy!

 

This is progress, but I wonder if designers ever get the opportunity to extract maximum performance on currently available sizes, AMD managed to squeeze a lot of extra performance (in percentage terms from larger formats than Intel - if they all got stuck on say 14nm for 5 years, what would the designers be able to squeeze out of it?

Moore's law is great, but this has probably stifled efficiency in design as they're always designing for the next smaller fab process.

 

Each chip is gonna cost a LOOOOOOOOOOOoooooooooot

 

Also, I thought that (as Gareth has already implied) that 10 nm production was running into physics limitations. 5 and 3 nm aren't going to magically be easier.

 

http://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/

If you want to torture yourself with hundreds of pages.

But the gist of it is that essentially the R&D departments of Intel, Samsung, TSMC and so on have been in "desperate struggle to find workaound for limitations" mode for over a decade already and its not going to get any easier and that things like for example strained silicon or tri-gate transistors aren't much more than absurdly expensive bandaids in the desperate struggle to stay away from physical limitations.

But in the past they always found ways around the problems, so there is still hope.