News UltraSoC announces Bristol engineering facility plans

bit-tech · 14 Sep 2017

Credits RISC-V for its growth.
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Corky42 · 14 Sep 2017

When the article talks of open source is that the same sort of open source that instantly springs to mind, as in anyone can contribute changes, as in a collaborative driven design of the architecture, as in this bit should go hear, this bit needs changing.

If so that sounds really cool, I wouldn't have a clue what's what but it must be really interesting if you do.

Anfield · 16 Sep 2017

@Corky42 Not sure how deep you want to delve into things, but the problem mentioned in the article linked below is one of the issues this whole Risc-V thing is trying to solve:

The advent of massively integrated, multimillion-instance IC designs is driving the demand for ever-faster design convergence at a time when semiconductor companies are facing unrelenting time-to-market pressures that mandate ever-shorter tapeout schedules. Register transfer level (RTL) code for these “gigascale” systems-on-chip is often developed by geographically-dispersed teams and combined with third-party IP and blocks from previous designs that have been augmented to meet the needs of the current design. Only after the RTL and reference macros and libraries have been fully defined and are consistent with each other can designers actually begin the implementation process—comprised of RTL synthesis, design planning and place-and-route (P&R) tasks—that will ultimately determine if their design goals can indeed be met.

By this time, however, decisions about the micro-architecture have already been made and designers are essentially locked-in to their early choices. If the design does not meet its timing, area, power, test and routability requirements, substantial resources will need to be applied to achieve design closure. In extreme cases, even significant changes to the RTL are needed, though typically most of the effort is focused on the synthesis and P&R tasks. The process of convergence, characterized by time-consuming design iterations between synthesis and P&R, can consume a large fraction of total design implementation time.
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http://www.eetimes.com/author.asp?section_id=36&doc_id=1287656

Of course the potential with open source regarding HW / ISA extends beyond whats mentioned, but its a start.

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News UltraSoC announces Bristol engineering facility plans

bit-tech Supreme Overlord Staff Administrator

Corky42 What did walle eat for breakfast?

Anfield Well-Known Member

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News UltraSoC announces Bristol engineering facility plans

bit-tech Supreme Overlord Staff Administrator

Corky42 What did walle eat for breakfast?

Anfield Well-Known Member

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