Name is fairly obvious Code Name - This is what the core is referred to Willamette was the first generation P4 core Brand ID - same as code name IIRC Package - The pin configuration of the processor. In this case, it's Pin Grid Array 478 Technology - The size of a single transistor in the core. 18-microns in your case (current processors are 13-microns) Specification is obvious Family and Model are basically the numerical represenations of what I said above Stepping - Cores get continually refined as their manufactured. One stepping might be slightly cooler or overclock better than its previous stepping. This is not the same as a changing the core however Instructions - These are the types of SIMD (Single Instruction, Multiple Data) protocols supported (basically shortcut commands for running multiple instructions for data) Core speed - This is how fast the processors internal operations are running Multiplier - Multiplier along with the FSB determines core speed FSB - Front Side Bus. How fast the processor communicates with other peripherals Bus Speed - This is the effective speed of the FSB. The Pentium 4 sends out 4 bits of data per clock cycle, so it transfers the same amount of data as if it only sent out 1 bit per cycle @ 400MHz. L1 Data - This is the memory closest the processor die for storing data L1 Trace - Your guess is as good as mine Level 2 - same as L1, except farther from the core and much larger Explanation on processor cache: the processor is a data hungry device. It runs best when it has data right on hand to process. L1, L2 and L3 (on some procs) caches provide really quick access to data. As the level # increases, the size and distance from the processor increases. The farther away it is, the more time it takes for the processor to retrieve that data.
