cpu question, involving instructions per cycle, per second, etc.

hi guys, i have some questions for you about cpus
ok, our comp. teacher at school gave us this homework for extra points, here it goes:


it is well known that MHz are not a trusty way to stablish a cpu's performance. if we take the simple performance formula...
a) how many instructions per second (ips) should an intel pentium 4 2GHz cpu perform?
b) how many instructions per second (ips) should an amd athlon xp 2000+ cpu perform?
c) what formula is used here?


so.. i have been reading a lot on the net, also i have read some post at bittech (some are just hilarious -whypick1's ones haha), and came with the following results:




__________________________________________________
a) intel pentium 4 2GHz
(frequency clock)x(operations per cycle) = instructions per cycle

frequency clock: 2000Mhz
operations per cycle: 6

so.. (2000)x(6) = 12,000 IPC

1 cycle per second = 1 MHz
so.. (Instructions per cycle)x(frequency clock) = Instructions per second
(12,000)x(2,000) = 24,000,000 Instructions per second <---------- answer for intel pentium 4 2GHz
__________________________________________________


__________________________________________________
b) amd athlon xp 2000+
(frequency clock)x(operations per cycle) = instructions per cycle

frequency clock: 1600Mhz
operations per cycle: 9

so.. (1600)x(9) = 14,400 IPC

1 cycle per second = 1 MHz
so.. (Instructions per cycle)x(frequency clock) = Instructions per second
(14,400)x(1,600) = 23,040,000 Instructions per second <---------- answer for amd athlon xp 2000+
__________________________________________________



__________________________________________________
c) formula
(frequency)x(operations per cycle) = instructions per cycle

(frequency)x(instructions per cycle) = instructions per second

so...
(frequency)x(frequency)x(operations per cycle) = Instructions per second
__________________________________________________


so, ara my answers correct or just wrong?
i would appreciate if anyone could help me with this homework

thanks

 

I dunno about the MIPS etc (looks good), but I can tell you that an Athlon 2000+ runs at 1667MHz, not 1600

P.S. Go Staind!

 

ok, now it makes sense..
so, the athlon xp 2000+ makes 25,010,0001 instructions per second.. i knew something was wrong cause i've read that the athlons xp runs like p4, and a little bit faster

athlon xp 2000+ > pentium 4 2ghz
athlon xp 2200+ > pentium 4 2.2ghz
ahtlon xp 2400+ > pentium 4 2.4ghz
and so on..

so.. does anyone have another opinion?

thanks for pointing that out Kameleon

/me listening tormented

 

yeah seems good. but the athlons are not rated to the pentium eqivalant (ie pentium4 1.4ghz > amd athlonxp 2400+). more the origional athlons (ie amd athlon 1.4ghz > amd athlonxp 1400+) because the origional athlons were measured in mhz like the p4.

just to complicate things further

 

how can you say that
just do the math, it's all in the numbers..
and i dont mean the megahertz.. as my first post says, "MHz are not a trusty way to stablish a cpu's performance"

amd cpu's do 9 instructions per cycle, while intel's do no more than 6 (exepct the HT ones)

but excuse me if im wrong, i just defend what i have been reading

 

i didnt need you to tell me how athlon xps worked in terms of instructions per cycle. im tellng you that athlons are not compared to pentium4s! there compared to the origional athlons. -its a common mistake that an athlon3200 runs the same as a pentium4 3.2-there non comparable.

it was just trivia! that may or may not help

 

er.. ok, sorry

but, do you think that my homework will be complete with this explanation (are the numbers correct?)?

thanks

 

P4 does 5 IPC last i heard, maybe that changed.

Also, it depends upon cache size, ram bandwidth and being able to keep the pipeline full = total performance.

 

This is part of the reasoning behind why the prescott doesn't perform better than the Northwood in pretty much anything other than encoding. Because the pipeline is never kept full

 

Just one thing...

Hz = cycles per second, 1 MHz = 1 Million cycles per second.

Now the bit I'm not so sure on...

AFAIK Some instructions take several operations to complete, others are "easier" and can take as few as one. Ignoring this and assuming that every instruction can be completed in one operation, MHz x operations per second = Million operations/instructions per second (MIPS). According to your answer, instructions per second is frequecy squared times operations per second.

I am very rusty on this and am probably wrong but if you could tell me the difinitions of operations, instructions and cycles (I'm assuming clock cycles), I'd be able to tell you the answer.

 

ok cibyr, look, i found this comparison chart:
http://www.cyberbreakcafe.com/jpj_computers/cpuvscpu.htm

the cpus im looking for are missing but i can get an idea from the chart

______________
amd athlon xp 2000+

1 hz = 1 cycle
1mhz = 1,000,000 cycles

speed in mhz = 1.667Ghz = 1,667Mhz = 1,667,000,000Hz

operations per clock cycle: 9
instructions per cycle: mhz x ipc = 14,400

if one hertz (one cycle) is done in one second; then i multiply IPC (14,400) times frequency (speed in hz [1,667,000,000]), and get instructions per second: 24,004,800,000,000 IPS


is this correct?
any suggestions?

[cibyr], i really could use your help here

 

Yup - 31 stage over 20something does even less IPC. I wonder what A64 is? Same as AXP?

 

I was wondering about the Pentium-M, since they seem to have blinding performance for their speeds...

 

They are "modded" Pentium 3's with added cache and some tweaks arent they??

 

Dunno, they're a lot faster than a P3. 50 seconds Super-Pi 1M on a 1.4GHz chip isn't bad...

 

it is shorter..7 stages i think.. not sure.. but anyways i am sure it is shorter

 

They are modified P3 cores with a huge 1meg L2 cache and 400mhz fsb like the original P4s. They also have SSE2 and P4 tweaks like netburst iirc. Basically its like an P4/P3 love child that's been genetically engineered to only have the best stuff. Problem is you can only use the 855 Pentium M mobile chipsets with them, but this should be sorted when they go desktop.

Gotta test my 1.7M with superpi and compare it to my 2.8C actually.

 

kk

Keeping with one operation per instruction (because operations required per instruction will change with what instructions you are using which will change with what you are doing)

Athlon XPs do 9 operations per cycle. Therefore

1,667Mhz x 9 operations = 15,003 Million operations/instructions per second (remember we are assuming that operations per second and instructions per second are the same because it is simply too complicated to do otherwise without detailed information that we would require from AMD and Intel about how long each instruction take - and there are a LOT of different instructions - and how often each instruction is used in normal usage)

Therefore an Athlon XP 2000+ does 15,003 MIPS or 15,003,000,000 IPS

Without hyperthreading a Pentium 4 does 6 operations per cycle.

2,000MHz x 6 operations = 12,000 Million operations/instructions per second.
Therefore a 2GHz Pentium 4 does 12,000 MIPS or 12,000,000,000 IPS

Forumla for IPS is Frequency (in Hz, cycles per second) x operations or instructions per cycle

All this is IGNORING many more fundamental aspects of a CPU's performance such as pipeline length, branch prediction, hyperthreading, caches, instruction sets etc etc

But the above should be enough to satisfy your teacher.

 

everybody is on the right track, but you all forgot that it uses one cycle to complete 1 stage of the pipeline, that is why a northwood core with its 20 stage pipeline is faster that a prescot core with its 31 stages and they had to double the L1 data cache and the L2 cache. That is also why the athlons perform so much better clock for clock because they have somewhere around a 12 stage pipe. so an athlon needs 12Hz to complete one instruction and a northwood needs 20Hz to complete one instruction and the prescot needs 31 Hz to complete that same instruction.

 

I knew this would get complicated...

No matter how long the pipeline is, this doesn't limit the maxium amount of instructions per second, merely how long it takes for each instruction to get through the pipeline - as one instruction leaves the 1st stage and moves onto the 2nd stage another instruction can start on the 1st stage. But it's more complicated than that. The "pipeline" isn't just like one long pipe; more like a network of branching pipes. The performance hit of longer pipelines happens when an instruction take a "wrong turn" and has to start again (this is where branch prediction comes in).

Since where talking about this stuff we might as well cover hyperthreading. Like I said before there are a lot of branches in the pipeline, so most of them are going to be unused at any given point in time. What hyperthreading does is let another thread's instruction of the moment have a go at the pipeline so long as the two threads/instuctions are using different resources. In a perfect world this would double the operations per cycle and therefore (M)IPS, but it only works that well in theory.

Mods: Maybe you could add some of the information in this thread to the FAQ?

[edit] Forgot to say that having a bigger cache boosts performance by having data and instructions ready to keep the pipeline full. When the cache is empty the system has to fetch the instructions/data from RAM while the CPU sits there effectively doing nothing. This is why celerons suck so much; their small cache leaves their long pipeline empty most of the time, even though it is the same pipeline that powers Pentium 4s.