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News IBM announces 5nm 'nanosheet' chip technology

Discussion in 'Article Discussion' started by Gareth Halfacree, 5 Jun 2017.

  1. Gareth Halfacree

    Gareth Halfacree WIIGII! Lover of bit-tech Administrator Super Moderator Moderator

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    Gareth Halfacree, 5 Jun 2017
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  2. perplekks45

    perplekks45 LIKE AN ANIMAL!

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    Does anybody have a link that provides further insight?
     
    perplekks45, 5 Jun 2017
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  3. Gareth Halfacree

    Gareth Halfacree WIIGII! Lover of bit-tech Administrator Super Moderator Moderator

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    The paper hasn't been publicly published yet, but there's a little more meat in the full press release. Not much, though: more fluff than tech.
     
    Gareth Halfacree, 5 Jun 2017
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  4. perplekks45

    perplekks45 LIKE AN ANIMAL!

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    Cheers!
     
    perplekks45, 5 Jun 2017
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  5. Corky42

    Corky42 Where's walle?

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    One thing i don't understand is why fabricating a structure (the transistor) from many sheets allows for a smaller structure versus the traditional layering, cutting, layering technique, is it a precision thing?
     
    Corky42, 6 Jun 2017
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  6. Gareth Halfacree

    Gareth Halfacree WIIGII! Lover of bit-tech Administrator Super Moderator Moderator

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    It doesn't; you can, as the article says, make FinFET on a 5nm process node. The trouble with FinFET isn't that it doesn't scale to 5nm, it's that it is inflexible.

    Back in the days of planar transistors, you could vary the feature size in different circuits on the chip according to your needs. When we switched to FinFET (and Intel's Tri-Gate Transistor), we lost that: each fin of a FinFET transistor is the same height as every other fin.

    IBM's nanosheet system goes back to allowing you to modify the feature size of individual parts of the chip, regaining flexibility we lost moving to FinFET. The article says as much 'ere:

    So, that's the reason for going nanosheet, not simply to scale to 5nm but to scale to a better 5nm.
     
    Gareth Halfacree, 6 Jun 2017
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  7. Corky42

    Corky42 Where's walle?

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    I would have thought the height could have been adjusted based on what parts of the design you apply and/or remove the masking agent, silicon, and all that stuff from, I'm not saying that's what they do just that i would assume it's possible if you didn't care about costs/time.

    It probably doesn't help that i don't understand why you'd want different heights on some transistors, if making the source, drain, and gates higher or lower brings advantages then why not apply that to all of them.
     
    Corky42, 6 Jun 2017
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  8. Gareth Halfacree

    Gareth Halfacree WIIGII! Lover of bit-tech Administrator Super Moderator Moderator

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    Nup, not possible. When you're building a FinFET chip, all the fins are the same height and you've no way of changing 'em regardless of cost or time invested.

    Because a design which is best for performance is not going to be best for power draw, and a design which is best for power draw isn't going to be best for performance. Not every part of a chip needs to be going balls-out all the time, so a FinFET chip built for performance wastes a lot of power that a nanosheet chip can save - which translates directly to lower power draw and/or higher upper speed limits.
     
    Gareth Halfacree, 6 Jun 2017
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  9. edzieba

    edzieba Virtual Realist

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    Or to put it another way: some transistors in your CPU need to be turning on and off some of the ~100W of power going into it. Others are dedicated to basic tasks while idling and you want them to use as little power as possible. If you're locked into one transistor fin size, you are either using overkill inefficient transistors and wasting idle power, or teeny tiny transistors you need massive arrays of for power switching (and are thus vulnerable to cascade failures).
     
    edzieba, 6 Jun 2017
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