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Level 3 cache?!?!?!?!

Discussion in 'Hardware' started by section8, 2 Jan 2007.

  1. section8

    section8 What's a Dremel?

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  2. ajack

    ajack rox

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  3. Guest-16

    Guest-16 Guest

    L3 is reserved for server based applications, especially on Intel boards where 2/4/8 CPUs have to navigate and go through a single northbridge to access main memory (this isn't a problem with opterons), so to compensate for the bottleneck they often have large extra caches bolted on to a "common core" since Xeons are based on P3/P4/Core architecture fundementally. Cache is EXTREMELY expensive to add to a CPU though. SRAM uses 4 transistors per bit which makes it fast but expensive.

    Adding levels of cache means you increase latency also: L1 is usually 1-4 clock cycles access time, and it's specific to instruction or data cache, but L2 is general cache for common data and has a ~7-15 clock cycle access latency depending on how it's made and predictively prefetched etc. L3 increases it again because it has to search in L2 and not find it beforehand and it goes up to 25-30 (I don't know the quoted low end) clock cycles. This is still faster than waiting for main memory but youv'e got to remember server chips are charged a hefty premium and people buy a lot of them so it's a good investment unlike consumer CPUs. Servers will often do the same operations again and again unlike consumer chips which means those instructions are more likely to be bunged into the huge onchip cache they have avaliable.

    Some P4-EEs which were effectively Xeon cores (Galatin for example) had onchip L3 cache. The 3.2EE was built on a 0.13 micron process and had 512k of L2 then 2meg of L3. It shows virtually no performance benefit, only in extreme situations.
     
  4. overdosedelusion

    overdosedelusion I mostly come at night, mostly..

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    I think i read that the AMD quads are supposed to be implementing L3 also
     
  5. Guest-16

    Guest-16 Guest

    Yea Im undecided as to how that's gonna pan out for them. Their L2s are all independent of each other, unlike C2D in which both cores have access to the same L2 so nothing is duplicated. L3 is shared on K8L but that means it costs more to implement and increases latency, plus it means that L2s are gonna be highly copied. Not a cheap solution to build, but quick to churn out.
     

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