Hardware The Secrets of PC Memory: Part 2

http://www.bit-tech.net/hardware/2007/12/17/the_secrets_of_pc_memory_part_2/1

In the second part of this series on PC memory technology, Ryan investigates the secrets behind mobile DDR and self-refreshing technologies, power down modes and chip packaging technologies.

 

Note to self: Don't attempt to decipher at 3am

 

LOL, it's 2am here but I'm thinking the same thing. I look forward to reading this tomorrow. Thanks Bit-tech & Ryan.

 

its only 10pm here and im thinking the same thing but ive been up since 4am (why cant cows milk them selves)

 

interesting, does stacking or other physical methods of increasing memory density increase the need for proper cooling?
ugh it's 4:37 here and I got an exam at 8 >_< this study break contained more information than my actual studying

 

I should think that the stacking of chips would make cooling things a little trickier although if something along the lines of the dominator cooling system were used this could be helped. By this I mean that as the Dominator uses the pcb to cool the underside of the chips, the stacked chips could be held together by some kind of thermal tape that would come out from between them and bond onto the heatsink. Just a thought.

 

dont try to decipher this 8.30AM Monday morning. read: MONDAY. bad idea.

but overall, amazing article. very informative. some stuff reminded me of college, some stuff ive never ever heard before, some stuff is just simply inspiring.

bravo.

 

FYI, I was probably drunk and tripping high on DMT when writing these stuff

m (*.*) m

A lot of the chip or module stacking are temporary solutions to a demand for larger capacity. These are usually used for advance server/storage systems. Performance is almost always secondary to signal reliability in these cases.

A lot of the stacking methods can produce signal irregularities at super high speed, so overclocking is a bad idea. That is why we don't see them as much in desktop market. The only stacking solution that works better is with the die, which we do see a lot in the desktop market.

Special PCB cooling solution (ie. Corsair Dominator series) is used to drain the heat downward in order to have a more even thermal expansion and contraction between Chip and PCB.

Micron D9 series on a cheaper standard PCB can often overclock as well with super expensive PCB, and we do find D9s in value/budget ram. Only problem is when the VDIMM is too high and the hot chip expand excessively, it cracks the connectors at the bottom.

 

some after thoughts...

About Moore's law
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Moore's Law is often referenced to the CPU, but the PC is a compilation of systems with the processor as the center. Hence, it is a requirement for all connected sub-systems to perform in-step and up to speed with the processor.

In the lab, we see many system instabilities attributed to the memory partly because of shrinking safety margins. On very high speeds like 1600MHz ++, if the motherboard and memory module is not engineered properly, the rig cannot run Dual-Channel in a stable manner.

These kinds of instability cannot be easily detected by Memtest86 and variants. Use Prime96's torture tests with emphasis on RAM.


On Chip fabrication
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Having lower power is technically a requirement with miniturization. With each generation of IC fabrication, the insulators are getting thinner between conducting elements. With a higher voltage, a thin insulator has problem preventing electrical current jumping across. A large margin of safety is dictated in the JEDEC standard in this respect, but not all DIMM makers follow them.

Overclocking with VDIMM tends to do many nasty things to the trace circuitries, specifically destroying the insulation. It looks like badly cooked cheese.

Interestingly, electro static literally create bomb craters on the conducting circuits.

 

It's the 3rd time in two days that I partially see the title of this thread or article and think I read "The secret of monkey island" only to go back and see it has nothing at all to do with it

 

Blimey Microns cell is small, a few years back I did an 8T bit cell layout, quite tough as these layouts don't follow the rules and require a lot of process knowledge to estimate OPC improvements, my cell was a lot bigger than this and took ages due to the effort involved in shaving every last nm off, funny when you think how simple it was, essentially a couple of inverters and some pulldowns you'd think it'd take 5 mins.

 

What I always find alarming is that we refresh DRAM in modern PCs at some ludicrous number of cycles a second, but if you actually try it on an electronics test bench, quite a lot of it will maintain its contents for... well, I've seen over a minute myself with nothing more than Vcc connected.

 

i think temperature may be a factor here. the warmer it gets, the faster the leakage.

Moreover, JEDEC always insisted on extra safety margins and leave nothing to chance.