Discussion in 'Article Discussion' started by Tim S, 27 Jan 2007.
Looks like good stuff, I sort of browsed the more informational parts, but it shows how complex our little CPUs are.
Thanks for the info.
Just speculation here but if Intel were to underclock and undervolt these then go into the mini-ITX market at a performance level at least equal to Via's best could they make it passively cooled? - I'm not expecting an answer but wondering how fast they could go with passive cooling. (I still remember a time before CPUs even had heat sinks)
Great article Tim.
Technically written whilst maintaining simplicity and remaining interesting
As Tyinsar says, what kind of thermal implications is 45nm going to have for laptop chips? One can only guess lower heat and less power meaning better battery life which then brings us back nicely to the article that Brett wrote
Sweet, I think that has to rate as one of my fav bit articles ever!
I've always had a strong interest in transistors since studying them at uni so it's good to keep up-to-date!!
When do you reckon these new chips will start shipping? 2h07?
Are these CPUs going to have HyperThreading? The Inquirer had a story saying that they would, but we all know what the inquirer is like.
I had hoped that all that HT nonsense was dead.
Tim, you are quite possibly mad, making this thread at 10 past 5 this morning
Anyway, I was impressed with the new mobile idea, it would mean laptops and alike would last even longer than current core 2's
Seeing what Intel's doing next is always interesting, it blows my mind to see just how clever Intel's techs are and how much they spend on R&D.
Looking at the die for Penryn, it looks like they'll be using the same sort of idea for the quad cores as Kentsfield, it's only a two core die.
On a related topic a friend of mine was doing a presentation on Intel (more importantly, SiO2 transistors. He showed a future possible design that was pretty clever, I'll try and find the image for you if I can.
hold on, am I right in thnking that 45nm should have a lower TDP than 65nm..??
Yes, at the same clock speed it will. Intel is happy with it's current power envelopes (and doesn't know how AMD's K8L is doing in terms of raw performance) so it is maintaining the same power envelopes and increasing performance.
The chips will start shipping in the second half of this year. Intel hasn't committed to a date yet (at least, they haven't given us a firm date yet). After all, the chips are still in a test phase.
I think I am fairly safe to put my ball firmly in the "there isn't a cat in hell's chance" court. That's at least the case with Penryn because it's based on Core. Next generation microarchitecture is a different thing entirely though and I can't really speculate.
Wouldn't it be better if they went a little bit of AMDs way? With all that cache taking up so much room... More space for actual processing, less space for bulky cache. How much do they really need that cache?
I think that there is definitely the scope for these chips to be put in mini-ITX boards. I believe performance would be high too - I'm hoping they'd be ULV (ultra low voltage) chips.
The other thing that I'm interested to find out is whether we'll see the same ULV dual-core parts (hopefully with similar performance to the current ULV models) with massively lower TDPs than current models, thus improving battery life massively in notebooks. I'd love to see something like the Sony VGA-SZ3XP (or the next incarnation) with the Santa Rosa platform and 10 hours+ battery life. It's already doing 7 1/2 hours battery life with a 2.13GHz Core 2.
I'm assuming you're meaning dedicated L1, dedicated L2 and shared L3 caches? I don't know - I reckon it's something we'll see in the next-gen microarchitecture when Intel's also got a native quad-core chip.
Yes, mainly the level 2 cache that takes up about half the chip, primarily for the reason that AMD chips don't seem to need all that much cache. Looking forward to the native quad cores.
It's a cheap way to keep up with Moore's law - after talking with Intel and reading a bunch of additional documentation, I felt that they were a bit obsessive with Moore's law.
The reason AMD doesn't need a lot of L2 cache is because the memory controller is on-die and thus has a much lower latency. Intel obviously doesn't have that benefit, so it hides latency with large cache. Of course, the question is whether we'll see similar scaling from 4MB to 6MB as we did with 2MB vs 4MB L2, or whether that cache is added for the sake of Moore's law - we'll have to wait until we've tested the chips for the answer to that.
Ah right, forgot about the latencies from lack of a memory controller. I think that amount of cache won't benifit dual cores all that much, for the quad, I can see a larger benifit, but that is just direct scaling.
The new FET design is quite good, and they will most likey find more combinations, probably with just one or two atomic layer for the gate.
Any more info on how they are planning for further shrinking the nm processes? In regard to transistor design.
Any word on whether they are going to start pushing up clocks again? We've been stuck on 2GHz for nearly 5 years now! I want GHz not cores
As far as I was aware, Moore has 'updated' his law at least twice since he first devised it. Mostly because earlier this decade, CPU's weren't moving as fast as were necessary to maintain it being truth.
...and who else thinks that using enormous amounts of L2 cache on the die to boost the transistor count is cheating slightly?
Did I miss it or is there no hint on the socket Penryn will use?
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