News TSMC launches WoW 3D chip packaging tech

IDK 7nm had reached volume production, last i heard it was at the sampling stage, I'm guessing someone like Apple already has dibs on it.

 

Ouch! That means the TSVs bonded to the substrate take away a massive amount of actual transistor area on the lower die.

With the 'normal' upper flip-chip die facing its FEOL layer to the top and the lower die having it stuffed down facing the sunstrate, this seems more aimed at mobile devices where dRAM dies are stacked on top of an SoC processor - moving the dRAM to the bottom of the stack and reducing the Z-height (smaller package, better thermals). I doubt this would see usage for bigger dies like desktop/laptop CPUs and GPUs: all the high-power logic would need to stay on the top die, so you would effectively be fabbing a second large die to shove underneath: doubling the chance of a defect killing a package (wafers bonded, the dies cut), and doubling the cost.

 

They aren't necessarily talking about the entire range of chips they produce, it is important to remember that TSMC has a lot of customers that buy chips that are no where near as hard to manufacture (or shrink) as pinnacles of engineering pr0n (Tesla gpu etc).

 

Indeed, I'm working on 180nm RF designs that are yet to be released nevermind in a fab, older techs still have a place for cost, yield and reliability reasons, often Analog designs with higher voltages or high frequency RF don't scale in size with process nodes unless they have big controllers/RAM/DSP etc, the digital areas typically yield the benefit of a node shrink, if 95% of a chip is analog the scaling of the process node doesn't matter too much unless you have a very large percentage of passives, resistors/metal capacitors