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Graphics Nvidia 1100/2000 Series Thread.

Discussion in 'Hardware' started by The_Crapman, 7 Aug 2018.

  1. GeorgeK

    GeorgeK Swinging the banhammer Super Moderator

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    I read a theory that the larger dies are a pain to manufacture and that the binning process is churning out plenty of chips suitable for the 2080 but not enough for the 2080 ti. The EVGA step up page is suggesting that the queue might be months long which would suggest that this isn't a short term shortage but instead might be a longer term thing
     
  2. Anfield

    Anfield Well-Known Member

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  3. Vault-Tec

    Vault-Tec Green Plastic Watering Can

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    It's not a theory really, just common sense. Dies are cut from round wafers and have areas where there are imperfections. The larger the die, the less you get per wafer and the more you have a chance of hitting a bad area. This is why AMD are so sorted with Ryzen, because they literally "glue" them together (only using Infinity Fabric). Intel's are single monolithic, so very expensive to make.

    So yeah, the bigger the die the more it costs and the more chance you have of it being a dud.
     
  4. Corky42

    Corky42 What did walle eat for breakfast?

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    It's a little more complex than that, certain parts of a wafer have higher failure rates than others, i would imagine Intel use the center for bigger, high performance, dies and the outside edges for smaller chips.
     
  5. edzieba

    edzieba Virtual Realist

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    It'd make sense, if they weren't using different chips.
    The TU104 is not just a cut-down TU102, it's a completely different die. Even the GPCs are not the same, TU102 (and TU106) use 12 SMs/GPC, while TU104 uses 8 per GPC.
     
  6. GeorgeK

    GeorgeK Swinging the banhammer Super Moderator

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    Oh ok then - I didn't realise that. Well back to the drawing board as to why all the delays then.
     
  7. loftie

    loftie Well-Known Member

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  8. Anfield

    Anfield Well-Known Member

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    Doesn't matter if it is an entirely separate die or not, yield always drops massively as die size goes up, so the theory that TSMC is simply struggling to supply Nvidia with sufficient chips for the TI is perfectly plausible (even if impossible to prove as exact yields for a specific product are impossible to come by).
     
  9. IanW

    IanW Grumpy Old Git

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    TL;DR

    [​IMG]
     
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  10. Corky42

    Corky42 What did walle eat for breakfast?

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    While i don't dispute that smaller die equals higher yields thing that's not how a wafer gets cut up, a single wafer hosts many different sizes depending on detected defects and the flexibility of how it can be segmented, you may get 10x 752mm2, 20x 652mm2, and 30x 552mm2 from a single wafer for example.
     
  11. edzieba

    edzieba Virtual Realist

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    The wafer layout is decided prior to fabbing, and will almost always be only hosting one type of die. You cannot 'cut' one die into another, you can only bin a die into different variants. e.g. All of the Ryzen line use one die (Zen), but binned differently to give different core counts (and clock speed ranges).

    Trying to cram multiple different dies onto a wafer would mean having to switch out the masks midway through the imaging process, that that introduces all sorts of new opportunities for defects to creep in: you need to take a wafer with a live photoetch, remove it from the scanner, place it in a cartridge, move it to storage, swap the mask, reclean the scanner, move the wafer back to the cleaning station, then load back into the scanner, then realign with the existing pattern. Through all this you need to avoid both exposing the wafer (because it has a live photoetch that you still need of sufficient quality to expose), not get any particles onto the wafer during any of the movement stages (and your cleaning must be FAR less aggressive than normal because you can't destroy that unexposed photoetch mask), AND you need a scanner that can align preceisely to an existing pattern. On a single scan mass the alignment is implicit because the wafer and scanner mechanism are not moved relative to each other (just the scan head).
    Having a bunch of dies of different sizes from the same wafer is extremely rare, and basically nonexistant for production runs (may occur for research and speciality devices like astronomy CCDs).
     
  12. Corky42

    Corky42 What did walle eat for breakfast?

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    No you can't 'cut' one die into another, but you can cut different sizes of dies from one wafer depending, as i said, the flexibility of how it can be segmented.

    Yes the wafer layout is decided prior to fabbing but that doesn't mean a defective 754mm2 die can't lose 209mm2 of defective wafer so you can make a 545mm2 die, or that you can't cut 100mm2 from a defective 545mm2 piece of wafer, depending, as i said, how you've deigned it.
     
  13. Vault-Tec

    Vault-Tec Green Plastic Watering Can

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    [​IMG]
     
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  14. edzieba

    edzieba Virtual Realist

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    No, you cannot. That's not how IC manufacturing works. At absolute best you can take a die and disable areas of it that do not work through efusing, but you cannot chop it down to any other size than the one it was designed to be.
    For example, this is why you will find the Zeppelin die with anything from 2 (EPYC 7251) to 8 cores enabled, but the die itself will ALWAYS be cut to identical dimensions.
     
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  15. Vault-Tec

    Vault-Tec Green Plastic Watering Can

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    Yup Ryzen dies are relatively cheap, and even if part of the die in that square was defective they can literally use it to balance the heat spreader on Threadripper.

    Lisa Su said at launch it was cheap and yields were high. This is why Intel hired Jim Keller lol, man's a genius.
     
  16. N17 dizzi

    N17 dizzi Well-Known Member

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  17. edzieba

    edzieba Virtual Realist

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    SOON.
     
  18. The_Crapman

    The_Crapman Don't phone it's just for fun.

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  19. adidan

    adidan Avatar is in season. See it while stocks last.

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  20. Sentinel-R1

    Sentinel-R1 Morse Monkey

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    Wonder if it comes with a mortgage offer?
     

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